7. Technical Field
The present invention relates to a parallel processing system in which a plurality of processors is interconnected in order to improve the performance of a computer, and more particularly, to a cluster system in which the number of nodes is small and which use Fibre Channel as an interconnection network.
2. Related Art
Since conventional parallel processing programs for business purposes are executed effectively by a symmetric multiprocessor (SMP) architecture, the SMP is used as a basic node and a plurality of nodes is interconnected in most parallel processing computers for business purposes. The following two methods are used in order to improve the performance of a system in which a plurality of nodes is loosely coupled, where the basic node is an SMP or a computer having a single processor.
One of them is to increase the number of nodes in the entire system while using a processor with conventional performance as the basic nodes. The other is to use a processor with improved performance. No matter which of the two methods is used, the characteristics of an interconnection network are an important factor which influences the performance of the entire system. The method of increasing the number of nodes is more dependent on the characteristics of the interconnection network.
Meanwhile, the computer industry is continuously trying to improve the performance of the processor. In the case of using a high performance processor, a cluster system in which the number of nodes is restricted to between 2 and 8 meets the needs of general customers with regard to price and performance. Therefore, it is preferable to develop both an interconnection network for connecting a small number of nodes (2 through 8) and an interconnection network for connecting a larger number of nodes in order to allow a system provider to meet the needs of various customers.
Two conventional methods for constructing the cluster system using Fibre Channel (FC) are a fabric method and a Fibre Channel Arbitrated loop (FC-AL) method. Hereinafter, it is assumed that an SMP is used for a basic node.
Where the number of nodes actually used in a parallel processing computer is less than the number of nodes provided by the interconnection network, the number of nodes can increase. However, this is ineffective with respect to the cost of the interconnection network. Namely, in the case of constructing the cluster system by the fabric method using a Fibre Channel switch, it is possible to easily increase the number of nodes as required, and to obtain a high throughput. However, when a switch required for constructing the fabric is expensive and the number of ports actually used is less than the number of ports provided by the switch, the ratio of the performance to the price of a system becomes worse.
The cluster system constructed by the FC-AL method has a disadvantage in that messages are delayed when nodes connected to the same loop simultaneously transfer a message since only one message can be transferred at a time.
The following patents are considered to be representative of the prior art and are burdened by the disadvantages discussed herein: U.S. Pat. No. 5,701,482 for a Modular Array Processor Architecture having A Plurality Of Interconnected load-Balanced Parallel Processing Nodes to Harrison et al., U.S. Pat. No. 5,689,646 for a Configuring Of Networked System To Permit Replacement Of Failed Modes And Selection Of Alternate Paths to Thourson, U.S. Pat. No. 5,649,106 for a Parallel Computer With Reconstruction Of Processor Clusters to Tsujimichi et al., U.S. Pat. No. 5,598,568 for a Multicomputer Memory Access Architecture to Frisch, U.S. Pat. No. 5,566,342 for a Scalable Switching Wiring Technique For Large Arrays Of Processor to Denneau et al., U.S. Pat. No. 5,471,623 for a Lambda Network Having 2.sup.M-1 Nodes In Each Of M Stages With Each Node Coupled To Four Other Nodes For Bidirectional Routing Of Data Packets Between Nodes to Napolitano, Jr., U.S. Pat. No. 5,471,622 for a Run-Time System Having Nodes For Identifying Parallel Tasks In A logic Program And Searching For Available Nodes To Execute The Parallel Tasks to Eadline, U.S. Pat. No. 5,465,369 for a Network Structure For Parallel Software Processing to Minca, U.S. Pat. No. 5,428,803 for a Method And Apparatus For A Unified Parallel Processing Architecture to Chen et al., U.S. Pat. No. 5,414,819 for an Optical Interconnection Network to Redmond et al., U.S. Pat. No. 5,390,336 for a C' Parallel Computer System Having Processing Nodes With Distributed memory With Memory Addresses Defining Unitary System Address Space to Hillis, U.S. Pat. No. 5,379,440 for a Parallel Processor With Arrays Of Clustered Processing Elements Having Inputs Separate From Outputs And Outputs Limited To A maximum Of Two Per Dimension to Kelly et al., U.S. Pat. No. 5,377,333 for a Parallel Processor System Having Computing Clusters And Auxiliary Clusters Connected With Network Of Parallel Networks And Exchangers to Nakagoshi et al., U.S. Pat. No. 5,361,363 for an Input/Output System For Parallel Computer For Performing Parallel File Transfers Between Selected number of Input/Output Devices And Another Selected Number Of Processing Nodes to Wells et al., U.S. Pat. No. 5,228,138 for a Synchronization Of Hardware Oscillators In A Mesh-Connected Parallel Processor to Pratt et al., U.S. Pat. No. 5,218,676 for a Dynamic Routing System For A Multinode Communications Network to Ben-Ayed et al., U.S. Pat. No. 5,197,130 for a Cluster Architecture For A Highly Parallel Scalar/Vector Multiprocessor System to Chen et al., and U.S. Pat. No. 4,739,476 for a Local Interconnection Scheme For Parallel Processing Architectures to Fiduccia.